Design of Low- Power High-Speed Error Tolerant Shift and Add Multiplier
نویسندگان
چکیده
Problem Statement: In this study, we had proposed a low power architecture for high speed multiplication. Approach: The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant. The proposed architecture enables the removal of input multiplexer, switching of adder cells and bypassing adder for zero bit values of the multiplier constant. The architecture makes use of down counter for tracking shift of partial products and multiplier bits. Results: When compared to the conventional architecture the simulation results for 8×8 multiplier shows that the proposed design reduces power consumption by 23.8% and delay by 35.6%. Conclusion: Enhanced performance of the proposed Error Tolerant shift and add multiplier in terms of power and delay makes it suitable for portable image processing applications where minimum percentage of error is tolerable.
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Modified 32-Bit Shift-Add Multiplier Design for Low Power Application
Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. ...
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